李拓，中国科学院计算技术研究所处理器芯片全国重点实验室（原计算机体系结构国家重点实验室）副研究员、硕士生导师。2014年在新南威尔士大学获得计算机科学与工程博士学位，之后留校从事研究工作，期间担任新南威尔士大学网络安全研究中心（UNSW IFCYBER）学术成员，于2023年加入中国科学院计算技术研究所。围绕计算机体系结构、硬件设计、安全、容错等领域，已发表论文20余篇，主要成果发表在IEEE Transactions on Computers、IEEE Transactions on Dependable and Secure Computing、Design Automation Conference(DAC)、International Conference on Computer-Aided Design(ICCAD)、Design Automation and Test in Europe(DATE)等领域内国际顶级会议和期刊。曾担任ASP-DAC 2024会议的技术委员会成员和分会场主席。长期担任CCS、DAC、ICCAD、IEEE TCAD、IEEE TDSC、IEEE TVLSI等领域内高影响力会议和期刊的审稿人，并参与RISC-V Rocket Chip等开源社区贡献。

个人主页：https://li3tuo4.github.io

[1] Sajid Hussain, Hui Guo, Tuo Li, Sri Parameswaran: MP-ORAM: A Novel ORAM Design for Multicore Processor Systems. IEEE Trans. Dependable Secur. Comput. 21(4): 3719-3733 (2024)

[2] Tuo Li, Sri Parameswaran: FaSe: fast selective flushing to mitigate contention-based cache timing attacks. DAC 2022: 541-546

[3] Hsu-Kang Dow, Tuo Li, Sri Parameswaran: HWST128: complete memory safety accelerator on RISC-V with metadata compression. DAC 2022: 709-714

[4] Hsu-Kang Dow, Tuo Li, William Miles, Sri Parameswaran: SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V. DAC 2021: 289-294

[5] Tuo Li, Bradley Hopkins, Sri Parameswaran: SIMF: Single-Instruction Multiple-Flush Mechanism for Processor Temporal Isolation. CoRR abs/2011.10249 (2020)

[6] Tuo Li, Muhammad Shafique, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran: Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors. IEEE Trans. Computers 66(4): 647-660 (2017)

[7] Tuo Li, Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran: Processor Design for Soft Errors: Challenges and State of the Art. ACM Comput. Surv. 49(3): 57:1-57:44 (2016)