1964年9月生于安徽省肥西县。1991年获中国科学院博士学位。1993年8月任北京大学计算机系副教授。2000年9月任中科院计算所研究员、博士生导师。现任计算所学位评定委员会副主席、计算机体系结构国家重点实验室（中国科学院计算技术研究所）常务副主任。中国计算机学会监事长、JCST副主编。获国家技术发明奖（2012）和国家科技进步奖（2015）。2013年入选国家百千万人才工程并获“有突出贡献中青年专家”称号、2014年入选“科技北京”百名领军人才培养工程；2016年获中国科协第七届“全国优秀科技工作者”荣誉称号

主要获奖:(1) 国家技术发明奖（二等奖/2012/排名第1）:星载微处理器系统验证-测试-恢复技术及应用(2) 中国质量协会质量技术奖（一等奖/2011/排名第1）:高性能处理芯片的测试和可靠性设计关键技术(3) 中国质量协会质量技术奖（可靠性管理优秀项目/2009/排名第1）:具有自修复能力的微处理器可靠性设计(4) 中国计算机学会“王选”奖（二等奖/2008/排名第1）:数字电路测试若干关键技术及其在微处理器测试中的应用(5) 中国科学院“教学成果奖”（一等奖/2008/排名第3）:面向计算机系统结构领域高级人才培养的课程体系建设(6) 北京市科学技术奖（三等奖/2008/排名第1）:数字电路实速测试和故障诊断技术及应用(7) 北京市科学技术奖（三等奖/2007/排名第1）:集成电路逻辑测试与验证基础技术(8) 中国科学院“杰出科技成就奖”（荣誉/2003/排名第5）:龙芯CPU研究集体(9) 中国科学院“自然科学奖”（二等奖/1992/排名第5）:测试方法研究及应用      主要荣誉:[1] “科技北京”百名领军人才培养工程（2014）:中科院计算所测试与容错技术创新团队[2] 国家“有突出贡献中青年专家”（荣誉称号/2013）[3] 国家“百千万人才工程”（2013）[4] 中国科学院“优秀研究生指导教师”奖（2012）[5] 中国科学院“朱李月华优秀教师”奖（2009）[6] 国务院政府特殊津贴（2009）[7] 中国科学院研究生院“集中教学突出贡献奖”（2008）[8] 中国科学院“优秀研究生指导教师”奖（2007）[9] 中国科学院“优秀研究生导师”奖（2006）[10] 中国科学院研究生院“优秀教师”（荣誉称号/2006）

部分学术著作:(1) 李晓维, 吕涛, 李华伟, 李光辉 著《数字集成电路设计验证: 量化评估, 激励生成, 形式化验证》, 科学出版社, 2010年5月, 411页(2) 李晓维, 韩银和, 胡瑜, 李佳 著《数字集成电路测试优化: 测试压缩, 测试功耗优化, 测试调度》, 科学出版社, 2010年6月, 344页(3) 李晓维, 胡瑜, 张磊, 鄢贵海 著《数字集成电路容错设计: 容缺陷/故障, 容参数偏差, 容软错误》, 科学出版社, 2011年4月, 433页　　部分期刊论文:[1] Y. Fang, H. Li, Xiaowei Li, “Lifetime Enhancement Techniques for PCM-Based Image Buffer in Multimedia Applications”, IEEE Transactions on VLSI Systems, Vol.22, No.5, May 2014, pp.1450-1455[2] J. Ye, Y. Hu, Xiaowei Li, Wu-Tung Cheng, Yu Huang, and Huaxing Tang, “Diagnose Failures Caused by Multiple Locations At-a-Time”, IEEE Transactions on VLSI Systems, Vol.22, No.4, April 2014, pp.824-837[3] K. Huang, Y. Hu, Xiaowei Li, “A Reliability-Oriented Placement and Routing Algorithm for SRAM-based FPGAs”, IEEE Transactions on VLSI Systems, Vol.22, No.2, Feb 2014, pp.256-269[4] B. Fu, Y. Han, H. Li, Xiaowei Li, “ZoneDefense: A Fault-Tolerant Routing for 2D Meshes Without Virtual Channels”, IEEE Transactions on VLSI Systems, Vol.22, No.1, Jan 2014, pp.113-126[5] Y. Zhang, H. Li, Xiaowei Li, “Automatic Test Program Generation Using Executing Trace Based Constraint Extraction for Embedded Processors”, IEEE Transactions on VLSI Systems, Vol.21, No.7, July 2013, pp.1220-1233[6] Z. He, T. Lv, H. Li, Xiaowei Li, “Test Path Selection for Capturing Delay Failures under Statistical Timing Model”, IEEE Transactions on VLSI Systems, Vol.21, No.7, July 2013, pp.1210-1219[7] S. Jin, Y. Han, H. Li, Xiaowei Li, “Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction”, IEEE Transactions on VLSI Systems, Vol.21, No.5, May 2013, pp.821-833[8] Y. Chen, L. Zhang, Y. Han, Xiaowei Li, “Thermal-Constrained Scheduling for Interconnect Energy Reduction in 3D Homogeneous MPSoCs”, IEEE Transactions on VLSI Systems, Vol.21, No.2, Feb. 2013, pp.239-249[9] S. Pei, H. Li, Xiaowei Li, “Flip-flop Selection for Partial Enhanced Scan to Reduce Transition Test Pattern Volume”, IEEE Transactions on VLSI Systems, Vol.20, No.12, Dec. 2012, pp.2157-2169[10] S. Pei, H. Li, Xiaowei Li, “A High-Precision On-Chip Path Delay Measurement Architecture”, IEEE Transactions on VLSI Systems, Vol.20, No.09, Sept 2012, pp.1565-1577[11] S. Pan, Y. Hu, Xiaowei Li, “IVF: Characterizing the Vulnerability of Microprocessor Structures to Intermittent Faults”, IEEE Transactions on VLSI Systems, Vol.20, No.05, May 2012, pp.777-790[12] X. Fu, H. Li, Xiaowei Li, “Testable Path Selection and Grouping for Faster Than At-Speed Testing”, IEEE Transactions on VLSI Systems, Vol.20, No.02, February 2012, pp.236-247[13] M. Zhang, H. Li, Xiaowei Li, “Path Delay Test Generation Toward Activation of Worst Case Coupling Effects”, IEEE Transactions on VLSI Systems, Vol.19, No.11, November 2011, pp.1969-1982[14] Y. Zhang, H. Li, Y. Min, Xiaowei Li, “Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects”, IEEE Transactions on VLSI Systems, Vol.19, No.10, October 2011, pp.1787-1800[15] G. Yan, Y. Han, Xiaowei Li, “SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation”, IEEE Transactions on VLSI Systems, Vol.19, No.9, September 2011, pp.1627-1640[16] G. Yan, Y. Han, Xiaowei Li, “ReviveNet: A Self-adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation”, IEEE Transactions on Computers, Volume 60, Issue 9, September 2011, pp.1219-1232[17] D. Fan, Xiaowei Li, G. Li, “New Methodologies for Parallel Architecture”, Journal of Computer Science and Technology, 26(4): 578-584, July 2011[18] G. Yan, Y. Han, H. Liu, X. Liang, Xiaowei Li, “Microfix: Using timing interpolation and delay sensors for power reduction”, ACM Transactions on Design Automation of Electronic Systems, March 2011, Vol. 16, No. 2, Article 16:1-21[19] Z. An, H. Zhu, C. Xu, Y. Xu, Xiaowei Li, “Synchronization of Linear Pulse-coupled Oscillators with Different Frequency”, IEEE Transactions on Industry Electronics, Vol.58, No.6, June 2011, pp. 2205-2215[20] Y. Yang, Y. Xu, Xiaowei Li, “A Loss Inference Algorithm for Wireless Sensor Networks to Improve Data Reliability of Digital Ecosystems”, IEEE Transactions on Industry Electronics, Vol.58, No.6, June 2011, pp. 2126-2137[21] J. Li, Q. Xu, Y. Hu, Xiaowei Li, “X-Filling for Simultaneous Shift- and Capture- Power Reduction in At-Speed Scan-Based Testing”, IEEE Transactions on VLSI Systems, Vol.18, No.7, July. 2010, pp.1081-1092[22] L. Zhang, Y. Han, Q. Xu, Xiaowei Li, H. Li, “On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems”, IEEE Transactions on VLSI Systems, Vol.17, No.9, Sept. 2009, pp.1173-1186[23] Y. Han, Y. Hu, Xiaowei Li, A. Chandra, Huawei Li, “Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for System-on-a-Chip”, IEEE Transactions on VLSI Systems, Vol.15, No.5, May 2007, pp.531-540