Journals:
[1] Wen Li, Ying Wang, Cheng Liu, Yintao He, Huawei Li, Xiaowei Li, “On-line Fault Protection for ReRAM-based Neural Networks,” IEEE Trans. on Computers (TC), early access, 2022.
[2] Yintao He, Ying Wang, Huawei Li, Xiaowei Li, "Saving Energy of RRAM-based Neural Accelerator through State-Aware Computing,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.41, No.7, pp. 2115 - 2127, 2022.
[3] Kaiwei Zou, Ying Wang, Long Cheng, Huawei Li, Xiaowei Li, “CAP: Communication-aware Automated Parallelization for Deep Learning Inference on CMP Architectures,” IEEE Trans. on Computers (TC), Vol.71, No.7, pp. 1626 - 1639, 2022.
[4] Ying Wang, Yintao He, Long Cheng, Huawei Li, Xiaowei Li, "A Fast Precision Tuning Solution for Always-On DNN Accelerators,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.41, No.5, pp.1236-1248, 2022.
[5] Yongchen Wang, Ying Wang, Huawei Li, Xiaowei Li, "An Efficient Deep Learning Accelerator Architecture for Compressed Video Analysis,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.41, No.9, pp.2808-2820, 2022.
[6] Shengwen Liang, Ying Wang, Cheng Liu, Lei He, Huawei Li, Dawen Xu, Xiaowei Li, “EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks,” IEEE Trans. on Computers (TC), Vol.70, No.9 pp. 1511 – 1525, 2021.  (Featured Paper in the September 2021 issue of IEEE TC)
[7] Ying Wang, Yongchen Wang, Cong Shi, Long Cheng, Huawei Li, Xiaowei Li, “An Edge 3D CNN Accelerator for Low Power Activity Recognition,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.40, No.5, pp.918-930, 2021.
[8] Ying Zhang, Krishnendu Chakrabarty, Zebo Peng, Ahmed Rezine, Huawei Li, Petru Eles, Jianhui Jiang, “Software-based Self-Testing using Bounded Model Checking for Out-of-Order Superscalar Processors,” IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD), Vol.39, No.3, pp.714-727, 2020.
[9] Liyang Lai, Hans Tsai, Huawei Li, “GPGPU-based ATPG System: Myth or Reality?” IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD), Vol.39, No.1, pp.239-247, 2020.
[10] Hang Lu, Mingzhe Zhang, Yinhe Han, Huawei Li, and Xiaowei Li, “Architecting Effectual Computation for Machine Learning Accelerators,” IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol.39, No.10, pp.2654-2667, 2020.
[11] Aijiao Cui, Mengyang Li, Gang Qu, Huawei Li, “A Guaranteed Secure Scan Design based on Test Data Obfuscation by Cryptographic Hash,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.39, No.12, pp.4524-4536, Dec. 2020.
[12] Ying Wang, Huawei Li, Long Cheng, Xiaowei Li, "A QoS-QoR Aware CNN Accelerator Design Approach,” IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD), Vol.38, No.11, pp. 1995-2007, 2019.
[13] Yun Cheng, Huawei Li, Ying Wang, Xiaowei Li, “Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug,” IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD), Vol.38, No.4, pp. 767 - 779, 2019
[14] Ying Wang, Huawei Li, Xiaowei Li, “A Case of On-chip Memory Sub-system Design for Low-Power CNN Accelerators,” IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD), Vol.37, No.10, pp.1971-1984, 2018.
[15] Ying Wang, Huawei Li, et al., “A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multi-Processors,” IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD), Vol.37, No.6, pp.1265-1277, 2018.
[16] Yun Cheng, Huawei Li, et al., “On Trace Buffer Reuse based Trigger generation in Post Silicon Debug,” IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD), Vol.37, No.10, pp.2166-2179, 2018.
[17] Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li, “Retention-Aware DRAM Assembly and Repair for Future FGR Memories”, IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD), Vol. 36, No.5, pp.705-718, 2017.
[18] Guihai Yan, Faqiang Sun, Huawei Li, Xiaowei Li, “CoreRank: Redeeming Imperfect Silicon by Dynamically Quantifying Core-level Healthy Condition of Manycore Processors”, IEEE Trans. on Computers (TC), Vol. 65, No.3, pp.716-729, 2016.
[19] Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li, and Sandip Kundu, “Abstraction-Guided Simulation Using Markov Analysis for Functional Verification,” IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD), Vol. 35, No.2, pp.285-297, 2016.
[20] Yanhong Zhou, Tiancheng Wang, Huawei Li, Tao Lv, Xiaowei Li, “Functional Test Generation for Hard-to-reach States Using Path Constraint Solving,” IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD), Vol. 35, No.6, pp.999-1011, 2016.
Conferences:
[1] Yintao He, Songyun Qu, Ying Wang, Bing Li, Huawei Li, Xiaowei Li, "InfoX: An Energy-Efficient ReRAM Accelerator Design with Information-Lossless Low-Bit ADCs,” Proc. IEEE/ACM 59th Design Automation Conference (DAC), 2022.
[2] Shengwen Liang, Ying Wang, Ziming Yuan, Cheng Liu, Huawei Li, Xiaowei Li, " VStore: In-Storage Graph Based Vector Search Accelerator,” Proc. IEEE/ACM 59th Design Automation Conference (DAC), 2022.
[3] Cangyuan Li, Ying Wang, Cheng Liu, Shengwen Liang, Huawei Li, Xiaowei Li, “GLIST: Towards In-Storage Graph Learning,” Proc. USENIX Annual Technical Conference (ATC), pp.225-238, 2021.
[4] Yongchen Wang, Ying Wang, Yinhe Han, Huawei Li, Xiaowei Li, “An Activity Analysis Architecture From Compressed Video Streams,” Proc. IEEE/ACM 58th Design, Automation Conference (DAC), 2021.
[5] Yintao He, Ying Wang, Yinhe Han, Huawei Li, Xiaowei Li, “TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning,” Proc. IEEE/ACM 58th Design, Automation Conference (DAC), 2021.
[6] Lei He, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li, “GCiM: A Near-Data Processing Accelerator for Graph Construction,” Proc. IEEE/ACM 58th Design, Automation Conference (DAC), 2021.
[7] Yongchen Wang, Ying Wang, Huawei Li, Yinhe Han, Xiaowei Li, “An Efficient Deep Learning Accelerator for Compressed Video Analysis,” Proc. IEEE/ACM 57th Design Automation Conference (DAC), San Francisco, CA, USA, 2020, Article No.: 167.
[8] Yintao He, Ying Wang, Xiandong Zhao, Huawei Li, Xiaowei Li “Towards State-Aware Computation in ReRAM Neural Networks,” Proc. IEEE/ACM 57th Design Automation Conference (DAC), San Francisco, CA, USA, 2020, Article No.: 73.
[9] Yongchen Wang, Ying Wang, Huawei Li, Shi Cong, Xiaowei Li, “Systolic Cube: A Spatial 3D CNN Accelerator Architecture for Low Power Activity Recognition”, Proc. IEEE/ACM 56th Design Automation Conference (DAC), USA, 2019, Article No. 210.
[10] Ying Wang, Shenwen Liang, Huawei Li, Xiaowei Li, “A None-Sparse Inference Accelerator that Distills and Reuses the Computation Redundancy in CNNs”, Proc. IEEE/ACM 56th Design Automation Conference (DAC), USA, 2019, Article No. 202.
[11] Wen Li, Ying Wang, Huawei Li, Xiaowei Li, “RRAMedy: Protecting ReRAM-based Neural Network from Permanent and Soft Faults During Its Lifetime,” Prof. IEEE Int. Conference On Computer Design (ICCD), 2019.   BEST PAPER AWARD
[12] Shengwen Liang, Ying Wang, Youyou Lu, Zhe Yang, Huawei Li, Xiaowei Li. “Cognitive SSD: A Deep Learning Engine for In-Storage Data Retrieval,” Proc. USENIX Annual Technical Conference (ATC), Renton, USA, pp.395-410, 2019.
[13] Ying Wang, Wen Li, Huawei Li, Xiaowei Li, “Leveraging DRAM Refresh to Protect the Memory Timing Channel of Cloud Chip Multi-Processors,” Proc. IEEE 2nd International Test Conference in Asia (ITC-Asia), pp.73-78, 2018. BEST PAPER AWARD
[14] Ying Wang, Huawei Li, Xiaowei Li, “Real-Time meets Approximate Computing: An Elastic Deep Learning Accelerator Design with Adaptive Trade-off between QoS and QoR,” Proc. IEEE/ACM 54th Design, Automation Conference (DAC), USA, June 2017, Article No. 33.
[15] Ying Wang, Jie Xu, Yinhe Han, Huawei Li, Xiaowei Li, “DeepBurning: Automatic Generation of FPGA-based Learning Accelerators for the Neural Network Family,” Proc. IEEE/ACM 53rd Design Automation Conference (DAC), USA, June 2016, Article No. 110.
[16] Ying Wang, Yinhe Han, Jun Zhou, Huawei Li, Xiaowei Li, “DISCO: A Low Overhead In-Network Data Compressor for Energy-Efficient Chip Multi-Processors”, Proc. IEEE/ACM 53rd Design Automation Conference (DAC), USA, June 2016, Article No. 37.
[17] Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li, “RADAR: A Case for Retention-Aware DRAM Assembly and Repair in Future FGR DRAM Memory,” Proc. IEEE/ACM 52nd Design Automation Conference (DAC), USA, June 2015, Article No. 19.
[18] Ying Wang, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li, “ProPRAM: Exploiting the Transparent Logic Resources in Non-Volatile Memory for Near Data Processing,” Proc. IEEE/ACM 52nd Design Automation Conference (DAC), USA, June 2015, Article No. 47.
[19] Binzhang Fu, Yinhe Han, Jun Ma, Huawei Li, and Xiaowei Li, “An Abacus Turn Model for Time/Space-Efficient Reconfigurable Routing,” Proc. International Symposium on Computer Architecture (ISCA), 2011, pp.259-270.